Comparators compare each bit of two words, an input word and a reference word, to determine whether the two words are identical, that is to determine whether each bit of the two words are identical or match. A masked comparator, with masking of individual bits, compares bits of the input word and reference words that are not masked to determine whether the unmasked bits of the two words are identical. A signal is generated indicating a match when the bits that are not masked in the input word and reference words match, without regard to whether the masked bits match. Otherwise a signal is generated indicating a match has not occurred.
One technique to compare the bits of an input word and a reference word in a masked comparator is disclosed in U.S. Pat. No. 4,958,140, the disclosure of which is incorporated by reference. This technique employs a two stage circuit. In the first stage a linear array of identical cells, one for each bit position in the words being compared, operates on one bit of each of the input word, the reference word and a mask word to determine whether there is a match for that bit position and to generate a comparison signal. The second stage combines the comparison signals from each cell in the first stage. The second stage can be realized using either a single logic gate with as many inputs as there are comparison signals from the first stage, or an inverted tree of logic gates. The output from the second stage is a match or no-match signal for the comparison of the input word and a reference word.
Specifically, for each bit position, a bit of the input word is combined with a bit of the reference word to produce an intermediate first stage output for that bit position. The intermediate first stage output for that bit position is then combined with the mask bit of the corresponding bit position to produce an output for each cell. As a result, the critical path from the input of bits of the input word, reference word, and mask word, to the output of the first stage of cells includes at least two gate delays, and the time required to obtain a final determination of the comparison even longer since the intermediate outputs from the first stage provide the inputs to the second stage.
While the known comparator technique achieves the desired result very rapidly, there remains a need to reach the final comparison result more quickly.